七段数码管

七段数码管

API

  • num : 十六进制数
  • light : 七段数码管显示方式

seven.v

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
module seven (
     input [3:0] num,
    output [6:0] light
);

    reg [6:0] temp;

    parameter
    // 七段数码管对应的16进制数
        NUM0 = 7'h3f,
        NUM1 = 7'h06,
        NUM2 = 7'h5b,
        NUM3 = 7'h4f,
        NUM4 = 7'h66,
        NUM5 = 7'h6d,
        NUM6 = 7'h7d,
        NUM7 = 7'h07,
        NUM8 = 7'h7f,
        NUM9 = 7'h6f,
        NUMA = 7'h77,
        NUMB = 7'h7c,
        NUMC = 7'h39,
        NUMD = 7'h5e,
        NUME = 7'h79,
        NUMF = 7'h71;

    always @(*) begin
        // 将 4 位二进制转换成对应的七段数码管
        case (num)
                4'b0000 : temp = NUM0;
                4'b0001 : temp = NUM1;
                4'b0010 : temp = NUM2;
                4'b0011 : temp = NUM3;
                4'b0100 : temp = NUM4;
                4'b0101 : temp = NUM5;
                4'b0110 : temp = NUM6;
                4'b0111 : temp = NUM7;
                4'b1000 : temp = NUM8;
                4'b1001 : temp = NUM9;
                4'b1010 : temp = NUMA;
                4'b1011 : temp = NUMB;
                4'b1100 : temp = NUMC;
                4'b1101 : temp = NUMD;
                4'b1110 : temp = NUME;
                4'b1111 : temp = NUMF;
                default : temp = NUM0;
        endcase
    end
    
    assign light = temp;

endmodule
编程 > Verilog语法
七段数码管
http://yjh-2860674406.github.io/2022/09/08/编程/Verilog/七段数码管/
Author
Ye JinHua
Posted on
September 8, 2022
Licensed under